The present disclosure relates to an interconnect structure, and particularly to an electromigration-resistant interconnect structure having a planar interface between a selective conductive cap and a dielectric cap layer on a metal line, and methods of manufacturing the same.
A metal line comprises a lattice of metal ions and non-localized free electrons. The metal ions are formed from metal atoms that donate some of their electrons to a common conduction band of the lattice, and the non-localized free electrons move with relatively small resistance within the lattice under an electric field. Normal metal lines, excluding superconducting materials at or below a superconducting temperature, have finite conductivity, which is caused by interaction of electrons with crystalline imperfections and phonons which are thermally induced lattice vibrations. In practice, copper and aluminum are most common metals that are employed as the material for metal lines in interconnect structures in a semiconductor chip.
When electrical current flows in the metal line, the metal ions are subjected to an electrostatic force due to the charge of the metal ion and the electric field to which the metal ion is exposed to. Further, as electrons scatter off the lattice during conduction of electrical current, the electrons transfer momentum to the metal ions in the lattice of the metal line. The direction of the electrostatic force is in the direction of the electric field, i.e., in the direction of the current, and the direction of the force due to the momentum transfer of the electrons is in the direction of the flow of the electrons, i.e., in the opposite direction of the current. However, the force due to the momentum transfer of the electrons is generally greater than the electrostatic force. Thus, metal ions are subjected to a net force in the opposite direction of the current, or in the direction of the flow of the electrons.
Metal lines are formed by a process called a damascene process, in which trenches and/or vias are formed in a dielectric layer and metal is inlaid into the trenches. Subsequently, excess metal above the topmost surface of the dielectric layer is removed by planarization, which can be effected for example, by chemical mechanical planarization. After planarization, the top surface of the remaining metal and the top surface of the remaining dielectric material are coplanar, i.e., located within the same horizontal plane. The remaining metal constitutes the metal lines that are embedded within the dielectric layer.
To reduce electromigration of the metal lines, a dielectric cap layer is deposited directly on the metal line. By atomically bonding to the uppermost surfaces of the material of the underlying metal line, the dielectric cap layer retards electromigration of the metal. In order to deposit the dielectric cap layer that atomically adheres to the underlying metal, however, it is necessary to remove non-metallic materials from the surface of the metal liners. Typically, the non-metallic materials are oxides of the metal of the underlying metal line, and may include additional contaminants. For example, if the underlying metal line is a copper line, the non-metallic oxide can be a surface layer of copper oxide, and if the underlying metal line is an aluminum line, the non-metallic oxide can be a surface layer of aluminum oxide. Without the removal of such non-metallic materials on the surface of metal lines, the dielectric cap layer can lose most of its effectiveness.
Thus, a “preclean” process is a required step before deposition of an effective dielectric cap layer. Because the metal oxides are bonded to the underlying metal line with good adhesion, significant energy must be imparted to dislodge the metal oxides and to expose metal atoms of the underlying metal line. Unfortunately, the same energy is applied to surfaces of exposed dielectric materials, which can suffer structural damages when significant energy is applied thereto. Typically, the preclean process employs plasma treatment with high energy density and/or physical sputtering by inert ions such as argon ions. Such a preclean process can significantly damage a dielectric material having a low dielectric constant, i.e., the dielectric constant of 3.9, which is a dielectric constant less than the dielectric constant of silicon oxide. Such materials include organosilicate glasses, which are SiCOH-based materials deposited by chemical vapor deposition (CVD). The degree of the damage to the exposed surface of the dielectric material increases in the case of porous dielectric materials, which are employed to form a dielectric layer having an ultra-low dielectric constant, i.e., a dielectric constant less than 2.4.
The damage to the exposed dielectric material during the preclean process has a significant adverse effect on TDDB reliability of the metal interconnect structure. The interface between the damaged underlying dielectric material and the dielectric cap layer includes many cavities and chemical properties that are conducive to electromigration between adjacent metal lines. The horizontal interface is coplanar with the top surfaces of the metal lines. TDDB failure in this case is causes by metal ions migrating under an electric field. (this is different from electromigration) Eventually, migration of metal continues along the horizontal interface between the damaged underlying dielectric layer and the dielectric cap layer during the lifetime of a semiconductor chip including this interconnect structure. Once sufficient migration occurs between adjacent metal lines, the two metal lines become electrically shorted, causing a circuit failure in the semiconductor chip. Thus, the damage to the underlying dielectric that occurs during the preclean process has a direct adverse impact on reliability, notwithstanding the benefit of enabling direct atomic contact between the metal of the underlying metal line and the dielectric cap layer and thereby retarding TDDB failure through a different mechanism.